A low power low noise high accuracy sensor IC

by 1974- Guo, Haidong

By Haidong Guo, Ph.D. Washington State University December 2006 Chair: George S. La Rue I investigated the design and implementation of low power low noise and high accuracy sensor IC for recording neural activity and studying sleep and other behavior in small animals. The sensor IC can acquire 16 electrophysiology signals in mice. It consists of 16 amplifier channels, a digital control circuit and a 16-bit 500 KSps charge redistribution self-calibrating successive approximation analog-to-digital converter (ADC). Each channel includes programmable gains from 12 to 250, a 7K Hz low-pass 2nd-order Butterworth filter and a track and hold. The integrated noise from 1 Hz to 7K Hz is 2.5 ?V for 0 V DC offset input, 3.76 ?V for 0.3 V DC offset input and 5.3 ?V for –0.3 V DC offset input. The power supply rejection ratios (PSRR) for VDD and VSS are 61 db and 51 db at 1K Hz. The +/-0.3 V DC input offset of each channel is cancelled with two 5-bit DACs controlling the positive input node of the 2nd gain stage and 3 rd gain stage op-amps. Total power dissipation is 1.2 mW for each amplifier channel with a +/- 1.5 V power supply. The 16-bit 500 KSps ADC has an input range of 2 V, a resolution of 16 bits, 6.2 mW power consumption and operates with +/- 1.5 V power supplies. Simulations show a signal-to-noise ratio of 90 dB for an effective accuracy of 15 bits in iv TSMC’s 0.25? CMOS process. A novel interleaving architecture and an improved comparator design contribute to reducing the power while maintaining the accuracy and speed. The ADC is intended to digitize the amplified neurophysiological signals from the companion 16-amplifier-channel IC. The amplifier channel IC die area is 19 mm 2 and the ADC die area is 7 mm 2 in TSMC’s 0.25? CMOS process. v