A high performance low power mesochronous pipeline architecture for computer systems

by Tatapudi, Suryanarayana Bhimeshwara.

Abstract (Summary)
by Suryanarayana Bhimeshwara Tatapudi, Ph.D. Washington State University May 2006 Chair: José G. Delgado-Frias In a conventional pipeline scheme each pipeline stage operates on only one data set at a time. The clock period in conventional pipeline scheme is proportional to the maximum pipeline stage delay. We propose a mesochronous pipeline scheme, where pipeline stages operate on multiple data sets simultaneously. In this scheme the amount of logic in a stage is more and number of stages is less compared to a conventional pipeline. The clock period in this scheme is proportional to the maximum pipeline stage delay difference, which means higher clock speeds are possible and number of pipeline stages is significantly less. In mesochronous pipeline scheme, clock distribution network is simple and load on it is less. A detailed analysis of the clock period constraints is provided to show the performance gain and Speedup of mesochronous pipelining over other pipelining schemes. In mesochronous pipeline scheme, overall current drawn is less, resulting in significant power savings and also less IR drop on power lines. Also, the variation in supply current (di/dt) drawn by clock network is significantly less in mesochronous scheme, thus power supply noise is less. An 8×8-bit multiplier using carry-save adder technique has been simulated in conventional and mesochronous pipeline approach using TSMC 180nm (drawn length 200nm). The mesochronous iv pipelined multiplier is able to operate on a clock period of 350ps (2.86GHz). This is a Speedup of 1.7 over conventional pipeline scheme and requires fewer pipeline stages and pipeline registers. The over-all power dissipation in mesochronous pipeline multiplier is less than 50% of the power dissipation in conventional pipeline multiplier. In the conventional implementation, power dissipation in clock network and pipeline registers is close to 80% of total power dissipation, while in the mesochronous implementation logic is dissipating more power. Also, the variation in current drawn by clock network in mesochronous scheme is less, causing less power supply noise. v
Bibliographical Information:


School:Washington State University

School Location:USA - Washington

Source Type:Master's Thesis

Keywords:pipelining electronics computers pipeline


Date of Publication:

© 2009 All Rights Reserved.