A hardware implementation of the imbedded reference signal algorithm system using a digital signal processing board
This dissertation proposes a hardware implementation of the IRS algorithm system by using the TI's DSP board called "TMS320C6701 bundled EVM". This research consists of three parts: the review and the study of the IRS algorithm system, the explanation of the hardware and criteria of chosen a suitable board, and the hardware implementation of the IRS algorithm system. This hardware implementation project is divided into two sections in terms of the implementation: the transmitter and the entire system, transmitter, channel, and receiver. So, we started with the system's transmitter implementation and then we implemented the system entirely at the hardware. At the transmitter implementation, we started writing the code in C language and then writing the assembly language for the linker command file, and we began the implementation with a very low value of the supersymbol's length and upgraded the system length gradually. Of course, these results led us to implement the receiver of the IRS system. So after doing many of modifications to the project, we implemented the IRS system at the hardware with different values of the supersymbol's length. Finally, we added the AWGN to the system and studied its performance experimentally.
School Location:USA - Ohio
Source Type:Master's Thesis
Keywords:hardware implementation imbedded reference signal algorithm system digital processing board
Date of Publication:01/01/2002