Details

The design and multiplier-less realization of a novel digital IF for software radio receivers

by Yeung, Kim-sang

Abstract (Summary)
(Uncorrected OCR) Abstract of thesis entitled

The Design and Multiplier-Less Realization of A Novel Digital IF for Software Radio Receivers

Submitted by Yeung Kim Sang

for the degree of Master of Philosophy at The University of Hong Kong

in August 2003

This thesis studies a new digital intermediate frequency (IF) architecture for software radio receivers (SRRs) and its design and implementation methodology. There are several differences between the proposed and conventional digital IF architecture. First of all, the sample rate converter (SRC) is performed immediately after the multistage decimators so that the programmable FIR filter can be replaced by a half-band filter (HBF) with fixed coefficients. This significantly reduces the implementation complexity. Secondly, the SRC is realized using a variable digital filter (VDF), instead of a fractional-delay digital filter (FDDF) in a conventional SRC. A new method for the optimal minimax design of this VDFbased SRC using semidefinite programming (SDP) is also proposed and compared with the traditional weighted least-squares method. Other implementation issues, such as the generation of the flexible clocking signal for different communication standards, and the calculation of the control parameter in the SRC, are also addressed. A new second-order compensator for compensating the passband droop of the cascaded integrator-comb (CIC) filter, and general low-pass anti-aliasing filters instead of the half-band filters (HBFs) in conventional receivers, are also proposed. The CIC compensator improves the passband

droop by a factor of four, and can be implemented with few additions. The generallowpass filters offer much better performance than HBFs in the conventional receivers.

To effectively reduce the system delay, the application of low-delay FIR and digital allpass filters to the proposed SRR is also investigated. The optimal minimax designs of these filters are formulated as an SDP problem, which allows zero magnitude constraint at (j) = 1r to be incorporated readily as additional linear matrix inequalities (LMIs). Design results show that system delay can be reduced significantly. Two approaches for the hardware implementation of the SRR are also considered. The first approach realizes the SRR using digital signal processors (DSPs), which are more suitable for software radio applications with large downsampling ratios. The second approach involves the multiplier-less hardware realization, which is more desirable in high-rate operations when the downsampling ratio is small. As most coefficients of the SRR are fixed, they can be implemented efficiently without multiplications using sum-of-powers-of-two (SOPOT) coefficients or Canonical Signed Digit (CSD). To further reduce the hardware complexities, the multiplier-block (MB) technique is employed to provide minimum adder realization. As a result, with the exception of a limited number of general multipliers required in the interpolation part of the SRC, the entire SRR can be implemented without any multiplications. The design of the proposed SRR is therefore relatively simple, as hardware complexity is minimized subject to the given frequency specifications and/or prescribed output accuracy, taking into account signal overflows and round-off noises. Design results and examples of the proposed SRR in supporting the GSM, W -CDMA, CDMA2000 and Hiperlan!2 standards are given to demonstrate the effectiveness of the proposed methodology.

Bibliographical Information:

Advisor:

School:The University of Hong Kong

School Location:China - Hong Kong SAR

Source Type:Master's Thesis

Keywords:digital filters mathematics radio receivers and reception signal processing techniques

ISBN:

Date of Publication:01/01/2004

© 2009 OpenThesis.org. All Rights Reserved.