Threshold Voltage Instability and Relaxation in Hydrogenated Amorphous Silicon Thin Film Transistors
The creation of extra defect states in the band gap of a-Si:H close to the gate dielectric interface, and the charge trapping in the silicon nitride (SiN) gate dielectric are the most commonly considered instability mechanisms of threshold voltage. In the first part of this work, the defect state creation mechanism is reviewed and the kinetics of the charge trapping in the SiN is modelled assuming a simplified mono-energetic and a more realistic Gaussian distribution of the SiN traps. The charge trapping in the mono-energetic SiN traps was approximated by a logarithmic function of time. However, the charge trapping with a Gaussian distribution of SiN traps results in a more complex behavior.
The change in the threshold voltage of a TFT after the gate bias has been removed is referred to threshold voltage relaxation, and it is investigated in the second part of this work. A study of the threshold voltage relaxation sheds more light on the metastability mechanisms of a-Si:H TFTs. Possible mechanisms considered for the relaxation of threshold voltage are the annealing of the extra defect states and the charge de-trapping from the SiN gate dielectric. The kinetics of the charge de-trapping from a mono-energetic and a Gaussian distribution of the SiN traps are analytically modelled. It is shown that the defect state annealing mechanisms cannot explain the observed threshold voltage relaxation, but a study of the kinetics of charge de-trapping helps to bring about a very good agreement with the experimentally obtained results. Using the experimentally measured threshold voltage relaxation results, a Gaussian distribution of gap states is extracted for the SiN. This explains the threshold voltage relaxation of TFT after the bias stress with voltages as high as 50V is removed.
Finally, the results obtained from the threshold voltage relaxation make it possible to calculate the total charge trapped in the SiN and to quantitatively distinguish between the charge trapping mechanism and the defect state creation mechanisms. In conclusion, for the TFTs used in this thesis, the charge trapping in the SiN gate dielectric is shown to be the dominant threshold voltage metastability mechanism caused in short bias stress times.
School:University of Waterloo
School Location:Canada - Ontario
Source Type:Master's Thesis
Keywords:electrical computer engineering
Date of Publication:01/01/2005