Abstract (Summary)
Partially reconfigurable devices have the ability to configure a portion of the device while the remaining portion of the device is still operational. This feature can be used to improve the performance of a pipelined design by overlapping the reconfiguration of a stage with the execution of previous stages. The above technique is called pipeline reconfiguration. By configuring pipeline stages one every clock cycle the constraint on the design size can be eliminated.This technique virtualizes the hardware and allows designs of any size to execute on finite sized devices. Virtual Pipelining uses pipeline reconfiguration and hardware virtualization to improve the performance of the design. This thesis presents a design flow for automatically synthesizing Virtual Pipelines on Virtex based FPGAs in order to improve the performance of a pipelined design. The input specification is a data flow graph with various arithmetic and logic operations. The input pipelined specification is split into a number of partial designs, each representing the status of the device during every clock cycle. While generating the partial designs, placement and mapping constraints are inserted into the design so that the design is placed column wise on the Virtex chip. The placement of the design is done so that it aids in the generation of partial bit-streams. In order to configure an individual pipeline stages, we developed a flow to generate partial bit-streams for pipeline stages. The flow uses guided place and route along with the JBits API to generate partial bit-streams. To control the flow of data, in and out of the pipeline stages, we presented a data flow controller that routes the data to and from the memory. And finally, to synchronize the reconfiguration and execution of the design, we presented a host controller to synchronize reconfiguration and execution of pipeline stages. To show the effectiveness of Virtual Pipelining, we executed our designs on the SLAAC-1V board. The results of our experiments indicated that there is a gain in throughput when a design is Virtually Pipelined when compared to the non-pipelined version. The gain in throughput is due to partial reconfiguration and pipelining. When the number of stages in the design is less than the number of stages that a device can fit, reconfiguration is not needed every clock cycle and hence the throughput gain is only due to increase in clock frequency because of pipelining.
Bibliographical Information:


School:University of Cincinnati

School Location:USA - Ohio

Source Type:Master's Thesis

Keywords:partial reconfiguration virtex based board virtual pipeline jhdl sblox serial blocks


Date of Publication:01/01/2001

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