Symmetrical residue-to-binary conversion algorithm, pipelined FPGA implementation, and testing logic for use in high-speed folding digitizers. /

by Monta, Ross Alan.; School (U.S.), Naval Postgraduate

Abstract (Summary)
The robust symmetrical number system (RSNS) can play a significant role in the reduction of encoding errors within a low-power folding analog-to-digital converter (ADC). A key part of this ADC design is the logic block that converts the symmetrical residues from each channel into a more convenient binary output. This thesis describes a robust symmetrical residue-to-binary conversion algorithm for moduli 1 7 m =, 2 8 m = and 3 9 m = (ADC dynamic range M = 126). Also described is a pipelined digital logic implementation for use in high speed programmable logic or application specific integrated circuits. To verify correct outputs of the robust symmetrical residue-to-binary conversion algorithm, a digital test circuit is described that generates the thermometer code (symmetrical residues) for the 3-channel ADC design.
Bibliographical Information:


School:The United States Naval Postgraduate School

School Location:USA - California

Source Type:Master's Thesis



Date of Publication:

© 2009 All Rights Reserved.