Prototipatge Ràpid de la Capa Física d'OFDM: cas HIPERLAN/2
This thesis presents the application of a new platform-based rapid prototyping methodology to the design of a communications subsystem, specifically the digital part of the physical layer of the HiperLAN/2 wireless protocol.
The main contributions of this research work are:
- Formulation and validation of a design methodology that directly transforms system level specifications to silicon platforms, while stressing heterogeneous multilevel verification.
- Exploration and implementation of new hardware architectures to improve some complex algorithms in the HiperLAN/2 chain, obtaining synthesizable models for the digital part of the physical layer of HiperLAN/2 transmitter and receiver, which were validated in the hardware architecture.
- Prototyping of the digital part of the physical layer of the HiperLAN/2 transmitter with a 12Mbits/s data transmission rate in a silicon platform, well-suited for WLAN systems. The aim of this prototype is to show the high productivity of the design methodology that ends into real platforms.
This dissertation is structured in four parts: fundamental concepts, rapid prototyping methodology, design of the physical layer, and transmitter prototyping.
The fundamental concepts part introduce OFDM modulation, and outlines the signal model as well as its advantages and disadvantages. Next, the standard wireless HiperLAN/2, that uses OFDM modulation, is presented. The working environment, network topology, physical layer, model complexity and burst types are discussed.
The chapter on rapid prototyping methodology for a WLAN system describes the design methodology proposed to prototype the transmitter and receiver of the digital part of the physical layer of HiperLAN/2, starting from the WLAN system requirements that lead to the selection of specific prototyping platforms. Current HW implementation capabilities are presented through the architecture of Virtex FPGAs, used as core hardware device. Next, we detail the WLAN system design methodology with the design flow and synchronization methods used. Two design flows are presented, a more general flow and a specific one, adapted to WLAN systems. These design flows detail different powerful options of heterogeneous multilevel verification, that profit from modern concepts of functional abstraction, orthogonality and heterogeneity.
The part about physical layer design of transmitter and receiver shows their structures and detail their computational components. Significant contributions have been proposed for IFFT/FFT, channel equalizer, synchronization, interleaver/deinterleaver and Viterbi modules. Synthesis results show their performance quality compared to current alternative designs. The overall results obtained from the transmitter and receiver models show also its global behavior and system level performance.
Transmitter prototyping describes changes applied to the transmitter model in order to map it into the specific silicon platform. Out of this complete prototype we extracted data from the spectrum analyzer and of transmitters power consumption that validate the proposed approach.
Advisor:Carrabina i Bordoll, Jordi; Martí i Puig, Pere
School:Universitat Autónoma de Barcelona
Source Type:Master's Thesis
Keywords:448 departament d enginyeria electronica
Date of Publication:05/11/2005