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POWER SUPPLY NOISE REDUCTION IN 90 NM USING ACTIVE DECAP

by Kulandaivelu Govindarajulu Thirumalai, Rooban Venkateh

Abstract (Summary)
On-chip supply voltage fluctuations are known to adversely affect performance parameters of VLSI circuits. These power supply fluctuations reduce drive capability, causes reliability issues, decrease noise margin and also adversely affect timing. Technology scaling further aggravates the problem as IR and Ldi/dt noise sources increase with each device generation. Current method used to reduce power supply variations uses an on-chip decoupling capacitors (decaps). These MOS capacitors utilize significant die area with about 15%-20% common for high-end microprocessors [4]. They also consume a considerable amount of power due to leakage and are prone to oxide breakdown during an ESD event because of reduced oxide thickness, making MOS capacitors unsuitable for technologies 90 nm and below. To improve the effectiveness of decap and reduce decaps area, a new active decap design is proposed for 90 nm technology.
Bibliographical Information:

Advisor:Robert B. Reese; Yaroslav Koshka; Raymond S. Winton

School:Mississippi State University

School Location:USA - Mississippi

Source Type:Master's Thesis

Keywords:electrical and computer engineering

ISBN:

Date of Publication:04/27/2009

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