Physical design with fabrication : friendly layout
Abstract of thesis entitled
"Physical Design with Fabrication-Friendly Layout"
for the degree of Doctor of Philosophy
at The University of Hong Kong
in November, 2004
Rapidly rising fabrication costs have so far prevented application-specific integrated circuit (ASIC) development into the sub-lOOnm critical dimension region. Rising costs are due to both the increasingly complicated mask fabrication process, requiring highly-optimized resolution enhancement technologies (RETs), and the more expensive design and process integration (DPI) required to embed highly-optimized RETs into the design flow.
In this study we present a novel low-cost process for ASICs for the sub-lOOnm region, including both physical design methodology and fabrication approaches. Using the current X,=193nm optical lithography system, the new process enables a critical dimension as small as 65nm, while keeping fabrication cost of ASICs at the same level as for the current 130nm technology.
The new process employs a fabrication-friendly layout in physical design, in which critical features are limited on a grid. The regular placement of features facilitates the optimization of the highly-optimized RETs and results in a resolution much higher than that of the conventional layout. At the same time, optimal for all strong-RETs, the grid placement also simplifies the physical design flow and separates physical designers from details of RETs. Although the radical constraints introduced by the grid placement have negative effects on circuit layout compaction, we develop a layout methodology for the fabrication-friendly ASICs to minimize the negative
effects and optimize circuit performance. The average layout area of ASICs designed in the new process is about 20% smaller than the original circuits using the 130nm technology.
Lithography methods for the fabrication-friendly ASICs are also developed, according to the new layout methodology. Although the regular placement of fine features enables an application of template masks, the current template lithographic approaches require too many exposures, leading to a decrease in yield. We introduce a novel template lithographic approach for fabrication-friendly ASICs. Without extra non-reusable masks, the new lithographic approach minimizes the number of exposures, while also improving the design flexibility of the fabrication-friendly ASICs. With all critical features designed by a reusable template mask, highly-optimized RETs, such as complex optical proximity correction (OPC), are no longer required for the sub-lOOnm region. The manufacturing cost for ASICs can therefore be kept at the current level.
School:The University of Hong Kong
School Location:China - Hong Kong SAR
Source Type:Master's Thesis
Keywords:application specific integrated circuits design and construction
Date of Publication:01/01/2005