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PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM

by QI, BIN

Abstract (Summary)
In modern microprocessors, more memory hierarchy and larger caches are integrated on chip to bridge the performance gap between high-speed CPU core and low speed memory. Large set-associative L2 caches draw a lot of power, generate a large amount of heat, and reduce the overall yield of the chip. As a result, large power consumption of the cache memory system has become a new bottleneck for many microprocessors. In this research, we analyze the performance of a location cache which works with a low power L2 cache system implemented by the drowsy cache technique. A small direct-mapped location cache is added to the traditional L2 cache system. It caches the way location information for the L2 cache access. With this way location information, the L2 cache can be accessed as direct-mapped cache to save both dynamic and leakage power consumption. Detailed mathematical analysis of the location cache power saving rate is presented in this work. To evaluate the power consumption of the location cache system on real world workloads, both SPEC CPU2000 and SPEC CPU2006 benchmark applications are simulated with the reference input set. Simulation results demonstrate that the location cache system can save a significant amount of power for all benchmark applications in L1 write through policy, and save power for benchmark applications with high L1 miss rate in L1 write back policy.
Bibliographical Information:

Advisor:

School:University of Cincinnati

School Location:USA - Ohio

Source Type:Master's Thesis

Keywords:cache low power l2

ISBN:

Date of Publication:01/01/2007

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