Performance Modeling Methodologies using PDL+ and ARC

by Vattyam, Priya

Abstract (Summary)
Analysis for Reconfigurable Computers (ARC) is a software environment in which systems can be modeled and executed. The models in the ARC system are described in a language called Performance Description Language (PDL+). A model of a system in PDL+ is described as a collection of components, attributes, and rules for computing these attributes. Functional attributes of a system describe the functionality of the system, whereas performance attributes are used to evaluate the characteristics of the system. Examples of some typical performance attributes of Very Large Scale Integration (VLSI) systems are clock frequency, area, power, and latency. ARC is a performance modeling environment and PDL+ provides a powerful yet concise notation for specifying generic performance measures of systems. Though PDL+ as a language had been developed a few years ago, performance modeling methodologies using PDL+ need to emerge. Most of the models written were test cases that demonstrated some selected features of the language. This was partly due to the continuous enhancements that were being made to the language and its environment. Another drawback was that a new language had to be learnt by potential users. The existing documentation has been in the form of language reference manuals and some basic examples, that were clearly not enough to motivate and guide a new user of the language. Through this thesis, we provide a comprehensive guide to the ARC system. We first highlight the various features of the ARC environment and the modeling language. We then demonstrate methodologies for developing performance models in the ARC system. The modeling methodologies are presented with the help of eight different case studies. These models provide good modeling insights to guide future model developers. Each of the case studies addresses different areas of VLSI systems and computer aided design (CAD) such as, high level synthesis, component libraries spatial partitioning, layout level delay estimation, reconfigurable processors, and power estimation. These models belong to various abstraction levels in the design flow and demonstrate modeling methodologies over different levels of abstraction. Some of the models have also been integrated with existing design flows. We elaborate the usage context, estimation procedure, and model development methodology for these models and also provide their annotated PDL+ implementations. We have also provided an accompanying diskette that contains the models, sample design files, and command files to execute them in the ARC system.
Bibliographical Information:


School:University of Cincinnati

School Location:USA - Ohio

Source Type:Master's Thesis



Date of Publication:01/01/2000

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