An Optimization Framework for Embedded Processors with Auto-Modify Addressing Modes

by Lau, ChokSheak

Abstract (Summary)
Modern embedded processors with dedicated address generation unit support memory accesses using indirect addressing mode with auto-increment and auto-decrement. The auto-increment/decrement mode, if properly utilized, can save address arithmetic instructions, reduce static and dynamic footprint of the program and speed up the execution as well. We propose an optimization framework for embedded processors based on the auto-increment and decrement addressing modes for address registers. Existing work on this class of optimizations focuses on using an access graph and finding the maximum weight path cover to find an optimized stack variables layout. We take this further by using coalescing, addressing mode selection and offset registers to find further opportunities for reducing the number of load-address instructions required. We also propose an algorithm for building the layout with considerations for memory accesses across basic blocks, because existing work mainly considers intra-basic-block information. We then use the available offset registers to try to further reduce the number of address arithmetic instructions after layout assignment.
Bibliographical Information:

Advisor:Pande, Santosh; Lee, Hsien-Hsin Sean; Uh, Gang-Ryung

School:Georgia Institute of Technology

School Location:USA - Georgia

Source Type:Master's Thesis



Date of Publication:12/08/2004

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