A New Memory Architecture

by Prasad, Skanda

Abstract (Summary)
Volatile Memory (RAM) is an important component of an Integrated Circuit application. The reliability and performance of the memory greatly influences the performance of the complete system. Static RAM is by far the most widely used embedded memory technology. As the technology scales down, the defects in the manufacturing process become more prominent and there is a need to account for these defects in the early stages of the design flow. The effect of these variations on the SRAM is more prominent, since the operation of SRAM depends on the balance of transistors. In this research, we present a new memory architecture that is much more robust when compared to the conventional architecture. Design of a new SRAM cell and the associated circuits is presented and the whole system in simulated in a predictive 22nm technology. The proposed architecture is more robust to process variations and consumes less leakage power. Even though the write power consumption is high, a more robust write operation is facilitated. The read power consumption of the new memory architecture is dependent on the data that is stored in the memory. Suitable encoding of data to reduce the power consumption forms the future work of this research.
Bibliographical Information:


School:University of Cincinnati

School Location:USA - Ohio

Source Type:Master's Thesis



Date of Publication:01/01/2008

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