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MODELING AND SIMULATION OF CLOCK DISTRIBUTION NETWORKS USING DELAY-LOCKED LOOPS

by RAVI, MAHESWARI S

Abstract (Summary)
With the advancement of nanometer scale processes in CMOS technologies, the demand for high performance VLSI systems continues to grow exponentially. The performance of a microprocessor is influenced by its clock distribution network. Clock skew penalizes the overall performance of the system. The task of minimizing clock skew in clock distribution networks continues to be critical in high speed circuits to maximize system performance. The objective of this research is to design a low skew clock distribution network by inserting Delay-Locked Loops with buffers along different clock paths of the clock distribution network. The delay-locked loops use delay lines which produce significantly lower skew and jitter than phase-locked loops. Clock skew can be reduced by employing DLLs in several appropriate places of the clock distribution network. The approach of distributing DLLs in a clock distribution network requires additional area but greatly improves the performance of VLSI systems.
Bibliographical Information:

Advisor:

School:University of Cincinnati

School Location:USA - Ohio

Source Type:Master's Thesis

Keywords:clock distribution networks delay locked loops buffers

ISBN:

Date of Publication:01/01/2006

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