Modeling 1/f Noise in a-Si:H Field-Effect Transistors
This work calculates the noise of the a-Si:H TFTs based on a simulation of operation of the TFTs and the hypothesis that the device noise is due to the intrinsic noise of the a-Si:H material. An a-Si:H TFT with an inverted-staggered structure has been simulated by numerically solving the fundamental transport equations for various gate and drain-source voltages. The drain-source curves derived from the simulation agree qualitatively with the experimental results: both the linear and saturated regions are observed. The low frequency noise was calculated based on the charge density distribution in the channel obtained from the simulation and the known dependence of the noise in the a-Si:H on the charge density, Hooges relation. The calculated noise power increases with the drain-source voltage and is inversely proportional to the gate voltage or the effective channel length. The curves agree qualitatively with the experimental results. The calculated noise power agrees quantitatively with the experiments when the scaling parameter in Hooges relation, , is set to . This value agrees with the experimentally determined value for a-Si:H. The results are consistent with the hypothesis that the low frequency noise in the a-Si:H TFTs is due to the material itself.
School:University of Saskatchewan
School Location:Canada - Saskatchewan
Source Type:Master's Thesis
Keywords:a si h field effect transistors 1 f noise
Date of Publication:10/17/2008