Mapping multimode system communication to a network-on-a-chip (NoC)
and the routes taken by all communications in the system. We validate the mapping results with a network-on-chip simulator (NoCSim). This thesis also investigates the cost associated with the interfacing of the components to the NoC. With the goal of reducing communication latency, we examine the packetization strategies in the NoC
communication. Three schemes of implementations were analyzed, and the costs in terms of latency, and area were projected through actual synthesis.
Advisor:Mahapatra, Rabi N.; Reddy, A. L. Narasimha; Walker, Duncan M. H.
School:Texas A&M University
School Location:USA - Texas
Source Type:Master's Thesis
Keywords:network on chip fixed cardinality transformation system heuristic
Date of Publication:12/01/2003