Abstract (Summary)
This research focuses on the software architecture of a reconfigurable computer (RC). Reconfigurable computers consist of field-programmable gate arrays (FPGAs). An application task for a reconfigurable computer is typically specified in a hardware description language such as VHDL or Verilog. This task can be divided into small independent subtasks, which, if executed in a specific order, will result in the completion of the task. In a typical application, the task in its entirety cannot be mapped onto a single FPGA due to the area limitations. The subtasks are small enough to individually fit into the FPGA device. The same FPGA can be reprogrammed many times to perform each of the subtasks. Thus a large task can be executed on a small FPGA. In this research, a self-contained set of CAD tools is developed for compiling a task onto a partially reconfigurable computer. Using the compiler developed in this research, starting from the register-transfer level (RTL) description of the task, partial bit-streams for the Xilinx Virtex FPGA can be generated. These bit-stream files can be used to reconfigure the partially reconfigurable processor to execute the task. High level synthesis is performed on the algorithmic specifications give in VHDL of the task to obtain the RTL description. The RTL description is composed of small sequential blocks called Basic Blocks. Data path synthesis is performed and a controller is generated for each basic block during high-level synthesis. A macro based synthesis approach is used for the synthesis of the data path. This approach eliminates the need for the time-consuming logic synthesis process. The macros used for implementation of the task are part of a pre-designed library based on the Xilinx JBits. The macros are implemented as Java classes. These macros are run-time parameterizable. A controller, along with combinational decoders, is used to control the data flow throw data path. The macros in data path and controller are placed and routed and finally, partial bit-streams are generated which can be used to configure the reconfigurable processor. Partial reconfiguration is used for the propagation of intermediate result of the subtasks via register macros on the chip. A host controller program is written to control execution of task on the reconfigurable computer. A set of benchmark tasks, written in VHDL, is implemented on the reconfigurable computer. The partial reconfiguration scheme is shown to be effective in reducing the reconfiguration time. Further, the macro based methodology is shown to be effective in reducing the compilation time.
Bibliographical Information:


School:University of Cincinnati

School Location:USA - Ohio

Source Type:Master's Thesis

Keywords:partial reconfiguration dynamic field programmable gate array fpga synthesis


Date of Publication:01/01/2002

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