Low power synthesis of BDD mapped circuits
Abstract (Summary)Power consumption is an important design constraint for circuits used in portable devices. In this thesis an analytic approach to minimize the power dissipation of Binary Decision Diagram (BDD) mapped digital circuits is presented. Our synthesis approach combines logic minimization, low power optimization and mapping to a Pass Transistor Logic (PTL) multiplexor circuit. The low power optimization procedure utilizes statistical properties for the input signals to reduce the estimated power dissipation. For BDD mapped circuits, the variable order of the underlying BDD heavily affects both the number of nodes (size) and the switching activity for each node. In turn, static power dissipation increases with circuit size, while dynamic power dissipation increases with switching activity and capacitive load. The capacitive load for a mapped node is modeled as the number of incoming edges. The cost model based on a PTL mapping is applied in a heuristic optimization procedure iteratively improving the overall cost by local variable exchanges. Three novel BDD based approximative methods for switching activity estimation are introduced. The first method assumes no temporal signal correlation. The second method assumes temporal correlation on the input signals only. Both of these simplifications allows the low power optimization to be carried out exclusively by local BDD operations. The third method accounts also for temporal correlation of internal signals in the circuit. The latter approach is refined at the cost of computation complexity, whereas the optimization is no longer local. The mapped circuits have in simulation (using a commercially available process model) shown reduced power dissipation characteristic. Furthermore a technique for extracting signal properties from synchronous Finite State Machine (FSM) implementations is described. All computations are performed using decision diagram techniques. As an application of this method, the extracted information is utilized in the presented low power synthesis procedure. Experimental results on MCNC (combinational) and ISCAS89 (sequential) benchmarks show significant reductions of the estimated power dissipation. The ISCAS89 results how an average reduction of 40 percent and up-to 90 percent on individual benchmarks.
School:Luleå tekniska universitet
Source Type:Master's Thesis
Date of Publication:01/01/2001