Low-complexity structures for digital symbol timing recovery
Abstract (Summary)Low Complexity Digital Implementation Structuresfor Symbol Timing Recovery Robert Morawski Symbol timing recovery (STR) is required in every digital synchronous communications receiver, since the output of the demodulator must be sampled periodically at syrnboI rate, at the precise sampling time instants in order to corredly recover the transmitted data. The major objective of this thesis is to present, analyze and prove feasibility of the new, low wmplexity. digital irnplementation structures for STR. The first presented digital structure is a feedback (FB) symbol timing recovery technique, which is based on the Costas loop principle. This technique requires only 5 constant multipliers and 7 adders, and has very low jitter feature. which is very desirable for high level modulation techniques. The structure, with its error tracking capabilities. is petfectly applicable for continuous mode communication systems, however, the required long acquisition tirne, rnakes this feedback STR not suitable for short burst mode communication systems. The feedforward (FF) STR techniques, have very short acquisition tirne, thus they are the perfect candidates for the short burst mode communication systems. and two such FF techniques are presented in this thesis as well. The first presented FF technique uses relatively high symbol over-sarnpling (16 samples per symbol) to achieve low implementation complexity (2 unsigned adders, 1 RAM block, and 1 serial magnitude cornparator). and acceptable jitter, with the help of only 4 symbols long training preamble. Due to high over-sampling rate, the technique is only applicable to communication systems with relatively low bit rate. In order to expand the applicability of this new over-sampling, technique to higher bit rate systems, an optional 'add-on " interpolation technique is presented, which can effectively reduce the over-sampling rate to a minimum of 3 samples per symbol. The cost for the improved performance is in the increased implementation wmplexity (additional 3 summers and 1divider). iii I would like to thank my mother and father, my girlfriend Edyta Walczak, al1 my family and my friends Arthur Winnik and Simmi Mangat, for their constant support and encouragement. I am also very thankful to my thesis advisor Dr. Tho Le-Ngoc, for providing me with the excellent research resources, for his highly valuable intellectual assistance, and for convincing me that tedious mathematical derivations are "worth the effort" complement to simulations and practical implementations. 1 would also Iike to thank Canadian lnstitute for TelecommunicationsResearch (CITR) Special Project with SR Telecom Inc. for their financial and technical support.
Source Type:Master's Thesis
Date of Publication:01/01/2000