Integrated upconverter design for WCDMA transmitter implemented in 90nm CMOS

by (Anosh Bomi), 1979- Davierwalla

DAVIERWALLA, ANOSH BOMI: Integrated Upconverter Design For WCDMA Transmitter Implemented In 90 nm CMOS. (Under the direction of Dr. Kevin Gard). Motivated by the overwhelming technology imperative to integrate radio frequency (RF) circuits along with digital baseband circuits on the same die, the fundamental objective of this research is to assess the potential of 90 nm CMOS technology for use in the RF transmit section of Wideband Code Division Multiple Access (WCDMA) cellular handsets while still meeting the exacting performance standards for the same. This thesis addresses the specific challenges associated with designing an upconverter for an integrated WCDMA transmitter implemented in 90 nm CMOS. The upconverter simultaneously performs quadrature modulation and direct upconversion of the baseband signal to the WCDMA transmit band located at (1920-1980) MHz. A double balanced mixer topology is used to perform frequency translation, with differential to single-ended conversion of the upconverted signal being effected by a current mirror at RF. To mitigate the crunch for voltage headroom, the upconverter design implements the baseband transconductor as a folded differential pair. This MOS differential pair transconductor is linearized based on ideas borrowed from the multi-tanh concept. At a rated RF output voltage of 60 mV (rms), the upconverter achieves an Adjacent Channel Leakage power Ratio (ACLR at ±5 MHz offset) of -56.1 dBc and an Alternate Channel Leakage power Ratio (ACLR at ±10 MHz offset) of -65.8 dBc. The conversion gain of each I and Q mixer is 0 dB, and the noise level in the WCDMA receive band at a +190 MHz offset is measured to be -139.5 dBc. While delivering this performance, the entire quadrature upconverter consumes a mere 1.7 mA from its nominal 1.2 V supply, thus proving to be an efficient and low-power design. Integrated Upconverter Design For WCDMA Transmitter Implemented In 90nm CMOS by Anosh B. Davierwalla A thesis submitted to the Graduate Faculty of North Carolina State University in partial satisfaction of the requirements for the Degree of Master of Science in Electrical Engineering Department of Electrical And Computer Engineering Raleigh 2005