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Integrated Circuit Interface for SAW Biosensors Applications

by Aggour, Khaled, MS


Page 81

Chapter 5: Simulation results of the SAW interfacing circuit 68

The SAW resonator electrical model is connected with the designed oscillator
circuit as shown in 5-1. The SAWR model ground pin is connected to the circuit
ground. The voltage supply (5V) is connected to the circuit.

Figure 5- 1 Test bed of the oscillator

Figure 5-2 shows the transient response of the reference oscillator. From the
transient simulation, it can be seen that the oscillator output has a DC component in
addition to its AC one.

Figure 5- 2 Reference oscillator transient response


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Chapter 5: Simulation results of the SAW interfacing circuit 69

To measure other oscillator specific parameters a Periodic Steady State (PSS)
was run. The maximum step size was set to 200ps as in transient simulation. Figure
5-3 shows the PSS AC magnitudes in voltages at different frequencies (up to fifth
harmonic).

Figure 5- 3 Reference oscillator PSS simulation Vout versus frequency

The DC component voltage is 3.057 V while the fundamental frequency was
found to be 228.727MHz and its peak amplitude is 1.442 V. The deviation of the
fundamental frequency from the SAW device resonant frequency (228.79MHz) is
explained in chapter 4 in the following equation

fm here equals 228.79 MHz

��� = (1 0.5 ���) eq.5.1

Substituting for fosc equals to 228.727 MHz and Cm= 4fF gives the parasitic
capacitance as in equation 5.2


C��� = 2C1 ���


= 2 × 4 fF 1 ���.���= 2.2 aF

���.��� eq.5.2

From the above equation, it can be seen that the effect of the parasitic
capacitance on the oscillator output is almost constant so the difference in SAW
resonant frequency will be reflected directly on the oscillator output frequency.


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Chapter 5: Simulation results of the SAW interfacing circuit 70

The fundamental frequency component has amplitude of 1.442V which is
capable of driving the mixer in a later stage. The largest harmonic has a magnitude
of 290.8mV. Figure 5-4 shows the magnitudes of harmonics in decibels.

Figure 5- 4 Reference oscillator PSS simulation Vout versus frequency (dB)

It is noticed from figure 5-3 that the difference between the fundamental
frequency magnitude and the first harmonic one is about 14dB. This value seems
insufficient to suppress the harmonic. Meanwhile the first harmonic appears to have
a large value; using a mixer and filtering the high frequency components of the
mixer output will attenuate all harmonics.

Increasing the motional capacitance of the SAW Cm will have the same effect
as applying a stimulus. Changing the capacitance from 4fF to 4.001fF will change
the resonator frequency from 228.790MHz to 228.762MHz i.e. a decrease of 28 kHz
occurs. The PSS simulation of the sensing oscillator is shown in figure 5-5.

The fundamental frequency of the oscillator is at 228.699MHz. Comparing
with the reference oscillator simulation results, it can be seen that frequency
difference f = (228.727 MHz-228.699 MHz) = 28 kHz which is the same value for
the frequency difference between SAW resonant frequencies.

The Relative Tolerance of the simulator (reltol) was set to 10-6 in order to
detect the small change in the oscillator frequency between reference and sensing
oscillators.


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Chapter 5: Simulation results of the SAW interfacing circuit 71

Figure 5- 5 Sensing oscillator PSS simulation Vout versus frequency

5.3 Mixer

The mixer output is the mixing of the two signals from reference and sensing
oscillators output ports. The mixed signals include different mixing of the signals
and their harmonics.

The test bed used for mixer simulation is shown in figure 5-6.

VDD=5V

XFAB
Bandgap cell

Reference

SAWR
Circuit model
Input IDT

Output IDT

Vbias =

2.6444V

Oscillator
Circuit in
XFAB cells
VDD=5V

Oscillator
Output

VDD=5V

GND

Vbias=

2.6444V VDD=5V

Mixer Circuit
in XFAB cells
Mixer Output

Sensing

SAWR
Circuit model
Input IDT

Output IDT

Oscillator
Circuit in
XFAB cells
Oscillator
Output

GND

Figure 5- 6 Mixer simulation test bed


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Chapter 5: Simulation results of the SAW interfacing circuit 72

The two oscillator outputs are connected as inputs to the mixer circuit and the
mixer output is extracted. The two SAW models, both reference and sensing has
different motional capacitance to take the chemical effect into account.

Choosing a small frequency difference between the sensing and reference
oscillators results in a very long simulation and causes the simulator to have a
convergence problem. As the reference SAW resonant frequency is 228.79 MHz, the
sensing oscillator frequency was chosen to produce a difference of 3MHz. The
sensing SAW resonant frequency is given as:


�����
��� 3푀퐻푧 = 225.79 푀퐻푧 eq.5.3

Calculating the motional capacitance for the sensing oscillator at this
frequency by:


=


(�������)

=

(�����.����)���.��


��

= 4.107푓퐹 eq.5.4

The transient simulation of the unfiltered mixer output is shown in figure 5-7.

Figure 5- 7 Mixer unfiltered output


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Chapter 5: Simulation results of the SAW interfacing circuit 73

To ensure the oscillation starts, 10 micro seconds was set in the transient
simulation as additional time to enable the oscillation to begin.

It is clear that the mixer has many high frequency components due to the sums
and differences between its two input signals and their harmonics.

The 2-stage RC low pass filter suppresses the undesired high frequency
signals; the low-pass filter transient output is shown in figure 5-8.

Figure 5- 8 Mixer output after Low-pass filter

It is clear that the high frequency contents of the output signal were removed.
The signal contains a large DC voltage (1.2V) and small AC amplitude (100mV).
The large DC signal adds additional 6mW power consumption. This component will
be suppressed via AC coupling as will be shown later.

Periodic Steady State (PSS) simulation is necessary for measuring the mixer
output behaviour. An initial time was set to enable a stable oscillation (5 Micro
seconds). A maximum step was set to 200ps as stated before. The mixer PSS
simulation is shown in figure 5-9.

The fundamental frequency component is at 3MHz with a voltage magnitude
of 188.9mV while the first harmonic (6MHz) is at 59.68mV.


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Chapter 5: Simulation results of the SAW interfacing circuit 74

Figure 5- 9 Mixer PSS fundamental voltage and harmonics

The simulated PSS response in decibels is indicated in figure 5-10.

Figure 5- 10 Mixer PSS Fundamental voltage and harmonics in dB


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Chapter 5: Simulation results of the SAW interfacing circuit 75

From the simulation results, it is clear that the fundamental component is 10dB
higher than the first harmonic. It is more likely that the mixer output frequency is in
the order of kHz. In such case, the filter will suppress the harmonics with a larger
attenuation. Moreover, the frequency-to-digital circuit is only sensitive to the
fundamental signal as the comparator will be switched either high or low.

The low-pass filter output signal and its delayed version are AC coupled and
applied to the comparator output as shown in figure 5-11.

Figure 5- 11 Mixer output conversion to a square wave

The aim of the RC delay circuit is to obtain a delayed version of the mixer
output signal. The difference signal changes its polarity and consequently the
comparator produces a square wave.

Figure 5- 12 Comparator positive and negative inputs


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Chapter 5: Simulation results of the SAW interfacing circuit 76

The two signals feed both positive and negative comparator input terminals.
The difference signal between the two terminals determines the comparator output
either as high or low. Figure 5-12 illustrates the process.

The signal has zero mean while it has amplitude of 75mV. This amplitude is
capable of driving the comparator.

The comparator output is the square wave required for the clock input to be
converted to a digital word.

The comparator square wave output signal is shown in figure 5-13.

Figure 5- 13 Comparator square wave output

5.4 Digital Conversion

The frequency of the square wave produced at the comparator output should be
converted to a digital word suitable for digital interface processing. A digital counter
is used with the comparator square wave feeding its clock. The counter is enabled for
10ms to achieve 100Hz resolution. The Enable signal is a clock of 50Hz frequency
and 50% duty cycle. The counter is generated using the arcoc03 cell (Appendix
A.3.4) clock cell (107.5 kHz) and a divider by 215 to achieve the required period of
20ms (Appendix B.2).


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Chapter 5: Simulation results of the SAW interfacing circuit 77

In order to avoid very long simulations; the comparator square wave output is
modelled in a mixed-signal simulation as a pulse source with 35% duty cycle as its
output is indicated in figure 5-14. The modelling of the pulse source in Verilog saves
the time for oscillator, mixer and sine to square modelling in Verilog domain and
provides the same simulation accuracy.

The chosen frequency of the comparator square output (counter clock) is 50
kHz. During the activation of the counting process (Enable signal output high); the
counter counts at the rising edge of the input clock (comparator square wave). The
counter output is incremented and maintains its value till another clock rising edge
occurs. The simulation of the counter transition at the clock rising event is illustrated
in figure 5-15.

When the Enable signal is logic low; the counter maintains the last counting
value and stops counting. The simulation of the counter during the full Enable cycle
is shown in figure 5-16.

After the completion of the Enable half period (10 ms), the counter output
should reflect the difference in the SAW device frequencies which is feeding the
counter clock.

The output of the counter is ‘01F3’ hexadecimal value which corresponds to
499 decimal. As stated before, the chosen frequency is 50 kHz which corresponds to
500×100 Hz.

The system uses synchronous reset at the rising edge of the counter as shown
in figure 5-16. So at the beginning of each measurement cycle (Enable signal cycle)
the counter output is reset to zero.

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