Document Text (Pages 111-120) Back to Document

Integrated Circuit Interface for SAW Biosensors Applications

by Aggour, Khaled, MS


Page 111

APPENDIX A: XFAB XC06 Process and Analogue Cells specifications 98

Parameter Symbol Typical Unit
P+ temperature coefficient TCDIFFP 1.3 10-3/K

Poly0 temperature
coefficient 1 TC1POLY - 0.2 10-3/K

poly1 temperature
coefficient 1 TC1POLY 1.1 10-3/K

poly1 temperature
coefficient 2 TC2POLY 1 10-3/K

metal1 temperature
coefficient TCMET 3.3 10-3/K

metal2 temperature
coefficient TCMET2 3.3 10-3/K

A2.3 Gate Capacitance

Parameter Symbol Typical Unit
gate oxide area
capacitance CGOX 2.76 fF/ µm
2
gate oxide breakdown

voltage BVGOX 13 V

NMOS gate - source/drain
overlap CGSDON 0.38 fF/ µm

PMOS gate - source/drain
overlap CGSDOP 0.3 fF/ µm

POLY1-MET1-MET2
sandwich area capacitance CSANDWT 0.07 fF/ µm
2
POLY1-MET1-MET2
sandwich perimeter
capacitance

CSANDWTF 0.05 fF/ µm

A2.4 Parasitic Capacitances

Parameter Symbol Typical Unit
poly1 - field area
Area CPFOX 0.061 fF/ µm
2
Perimeter CPFOXF 0.048 fF/ µm

metal1 - active area
Area CMDIFF 0.043 fF/ µm
2
Perimeter CMDIFFF 0.048 fF/ µm

metal1 - field area
Area CMFOX 0.027 fF/ µm
2
Perimeter CMFOXF 0.043 fF/ µm

metal1 - poly0/poly1
Area CMP 0.40 fF/ µm
2


Page 112

APPENDIX A: XFAB XC06 Process and Analogue Cells specifications 99

Parameter Symbol Typical Unit

Perimeter CMPF 0.047 fF/ µm
metal2 - active area
Area CM2DIFF 0.017 fF/ µm
2
Perimeter CM2DIFFF 0.040 fF/ µm

metal2 - field area
Area CM2FOX 0.013 fF/ µm
2
Perimeter CM2FOXF 0.038 fF/ µm

metal2 - poly0/poly1
Area CM2P 0.017 fF/ µm
2
Perimeter CM2PF 0.038 fF/ µm

metal2 - metal1
Area CMM 0.030 fF/ µm
2
Perimeter CMMF 0.045 fF/ µm

Coupling Capacitance
poly1 - poly1 CP1P1 0.038 fF/ µm

metal1 - metal1 CM1M1 0.057 fF/ µm
metal2 - metal2 CM2M2 0.074 fF/ µm

A.3 Analogue Cells

A.3.1 Band gap (abgpc01)
Parameter Description Typical Unit Conditions

VBGP

Output reference VDD=5V; T=25°C
1.281 V
voltage RL>10MΩ

VBGVTN

Output voltage for VDD=5V; T=25°C
2.668 V
bias cells No DC load

TCVBG
VDD = 4,5 to 5,5 V

Temperature RL=10MΩ
coefficient of ppm / °C
200 T = -40 to 20° C
VBGP 50 T = 20 to 85°C

VCVBG

Voltage coefficient

of
VBGP

+/-
1000 ppm / V
VDD = 4,5 to 5,5V;

T= -40 to 85°C
RL=10MΩ

CL Load capacitance 30 (max) pF

T = -40 to 85°C
VDD = 4,5 to 5,5 V
RL=10MΩ

VDD Supply voltage 5 V T= -40 to 85°C

IDD Supply current 29 µA

VDD = 4,5 to 5,5V;
T= -40 to 85°C


Page 113
APPENDIX A: XFAB XC06 Process and Analogue Cells specifications 100
A.3.2 Bias Cell (abiac01)
Parameter Description Typical Unit Conditions
IVBP
Current through
P-MOS 200.6 nA
VDD=5V; T=25°C
reference: abgpc01
IVBN
Current through
N-MOS 201.6 nA VDD=5V; T=25°C
reference: abgpc01
VBP Bias voltage for
P-MOS
VDD-
1.025 V VDD=5V; T=25°C
No DC load
VBN Bias voltage for
N-MOS 0.964 V VDD=5V; T=25°C
No DC load
TCIVBP
TCIVBN
Temperature
coefficient of
IVBP
IVBN
-1000
-1250 ppm / °C T = -40 to 85 °C
VDD = 4,5 to 5,5 V
VCIVBP
VCIVBN
Voltage
coefficient of
IVBP
IVBN
0.33
5 %/V VDD = 4,5 to 5,5V;
T= -40 to 85 °C
VDD Supply voltage 5 V T = -40 to 85 °C
IDD Supply current 6.5 µA VDD = 4,5 to 5,5V;
T= -40 to 85 °C
A.3.3 Comparator (acmpc02)
Parameter Description Typical Unit Conditions
VIO Input Offset Voltage 3 V VDD=5V;VCM=VDD/2;T=
25°C (absolute values)
VI Hysteresis 13,8 V VDD=5V; T=25°C
VIL Low Input Voltage 1.4 V VDD=5V; T=25°C
VIH High Input Voltage VDD-
0, 36 V VDD=5V; T=25°C
VOL Low Output Voltage 0 V VDD=5V; T=25°C;
RL=1MΩ
VOH High Output Voltage VDD V VDD=5V; T=25°C;
RL=1MΩ
TPD
Propagation
Delay Time
Rise
Fall
93,1
95.2 ns
VDD=5V;VCM=VDD/2;T=
25°C
RL=1MΩ; CL=0.5pF
50mV overdrive
PSRR Power Supply
Rejection Ratio 66 dB
VDD=5V;VCM=VDD/2;T
=25°C
(evaluated at DC)

Page 114

APPENDIX A: XFAB XC06 Process and Analogue Cells specifications 101

Parameter Description Typical Unit Conditions

VDD Supply voltage 5 V T=-40 to 85 °C

IDD Supply Current 74
3

µA
VDD=5V; T=25°C
Enabled
disabled

A.3.4 Oscillator (Clock) (arcoc03)
Parameter Description Typical Unit Conditions

FCLK Oscillator Frequency 10.06 kHz VDD=5V; T=25°C)

DC Duty Cycle 50 % VDD=5V; T=25°C)

TCFCLK

Temperature T= 0 to 85 °C
-3200 ppm/°C
Coefficient of FCLK VDD = 4,5 to 5,5V

VCFICLK
Voltage Coefficient of T= 0 to 85 °C
36 %/V

FCLK VDD = 4,5 to 5,5V

VDD Supply Voltage 5 V T= -40 to 85 °C

IDD Supply Current 3.8 µA VDD = 4,5 to 5,5V

T= -40 to 85 °C

A.3.5 Power On Reset (aporc02)
Parameter Description Typical Unit Conditions

VTH Threshold voltage 2.03 V VDD=5V; T=25°C)

TCVTH
Temperature coefficient T = 0 to 85 °C
of -2000 ppm/°C VDD=5V

VTHIGH / VTLOW

TPOR Delay time 5 µs VDD=5V; T=25°C

VDD Supply Voltage 5.0 V T = -40 to 85 °C

IDD Supply Current 1.8 µA
VDD = 4,5 to 5,5V;
T= -40 to 85 °C
In static mode


Page 115
APPENDIX A: XFAB XC06 Process and Analogue Cells specifications 102
A.3.6 Analogue to Digital Converter (aadcc01)
Parameter Description Typical Unit Conditions
RES Resolution 10 Bits
VDD=5V; T=25°C
VREF=VDD,
FCLK=1MHz
INL Integral
Nonlinearity 1,5 LSB
VDD=5V; T=25°C
VREF=VDD,
FCLK=1MHz
DNL Differential
Nonlinearity 0,5 LSB
VDD=5V; T=25°C
VREF=VDD,
FCLK=1MHz
VREFL
Low Reference
Voltage 0 V VDD = 4,5 to 5,5V;
T= -40 to 85 °C
VREFH
High Reference
Voltage Min. 1 V VDD = 4,5 to 5,5V;
T= -40 to 85 °C
FCLK Clock Frequency 1 MHz VDD = 4,5 to 5,5V;
T= -40 to 85 °C
TCONV Conversion Time 12 Clock
cycles
VDD = 4,5 to 5,5V;
T= -40 to 85 °C
VDDA
VDD! Supply Voltage 5 V VDD = 4,5 to 5,5V;
T= -40 to 85 °C
IDDA
Power
consumption
analogue part
185 µA
VDD=5V; T=25°C;
FCLK=1MHz
RES=0
RES=1 (stand-by
mode)

Page 116

APPENDIX A: XFAB XC06 Process and Analogue Cells specifications 103

A.3.7 Digital to Analogue Converter (adacc01)

Parameter Description Typical Unit Conditions
RES Resolution 10 Bits VREF=VDD=5V, T=25°C
INL Integral Nonlinearity 0.6 LSB VREF=VDD=5V, T=25°C

DNL Differential
Nonlinearity 0.2 LSB VREF=VDD=5V, T=25°C

TCONV Conversion Time 0.5 µs

VREF=VDD=5V, T=25°C
CLOAD=1pF
Low Reference 0 V

VDD = 4,5 to 5,5V;
VREFL

Voltage T= -40 to 85 °C
High Reference VDD = 4,5 to 5,5V;

VDD V

Voltage T= -40 to 85 °C

RIN

Resistance of Voltage
divider 9 T=25°C

ROUT Output Resistance 9 VDD=5V, T=25°C
VREFH

CLOAD Load Capacitance 1 pF VDD = 4,5 to 5,5V;

T= -40 to 85 °C

VDD Supply Voltage 5 V T= -40 to 85 °C


Page 117

APPENDIX B: VHDL Codes 104

APPENDIX B

VHDL Codes

B.1 16-bit Counter

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;
use STD.textio.all;
entity Counter16bit is
port( Clk,Reset,Enable: in Std_logic;
Count: out Std_logic_vector(15 downto 0)
);
end counter16bit;
Architecture Behavioral of Counter16bit is
signal Q: std_logic_vector(15 downto 0);
begin
process(Enable, Reset,Clk)
begin
if Enable='1' then
if rising_edge(Clk) then
if Reset='1' then
Q <= "0000000000000000";
else
Q <= Q + '1' ;
end if;
end if;
end if;
end process;
Count <= Q ;
end behavioral;


Page 118

APPENDIX B: VHDL Codes 105

B.2 Clock Divider by 215

Entity clock_divider_by_215 is
-- ---------------------------------------
Port ( Clk_in : In std_logic; -- Main Clock
Enable : In std_logic ;
Clk_out : out std_logic);
end;
-- ---------------------------------------
Architecture behavioral of clock_divider_by_215 is
-- --------------------------------------signal
Not_clk: std_logic;

begin
process (Clk_in,Enable)

variable Temp : std_logic_vector (9 downto 0);
variable One : std_logic_vector (9 downto 0);
variable Temp_out : std_logic;

begin
One:="0000000001";
if rising_Edge(Enable) then
Temp:= "0000000000";
Temp_out:= '1';
end if;
if (Enable='1') then
Not_Clk <= Not Clk_in;
if (rising_edge(Clk_in)) then
Temp:= std_logic_vector (unsigned(Temp)+Unsigned(One));
end if;
if falling_edge(clk_in) then
Temp:= std_logic_vector (unsigned(Temp)+Unsigned(One));
end if;
if (Temp= "0011010111") then -- reach 215 to send low output
Temp_out := '0';
else if (Temp= "0110101110") then --reach 430 to send high output
Temp_out:= '1';
Temp:="0000000000";
end if;
end if;
end if;
Clk_out <= Temp_out;
end process;
end behavioral;

B.3 System Temperature control

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
Entity system_temp_ctrl is -- system
generic (m : integer := 48;
-- 48 bit registers for arithmetic operations
n : integer := 24 );-- 24 bit registers for arithmetic operations
-- ---------------------------------------
Port ( Clk_in : In std_logic;
-- Main System Clock works at the rising edge


Page 119

APPENDIX B: VHDL Codes 106

Enable : In std_logic ;
-- Enable signal for the system to start calculation
Rst : In std_logic ;
-- Asynchronous reset for thesystem to set all values to their
defaults when powering ON
Calibrate_EN: In std_logic ;
-- Starts the calibration mode when the signal is high and computes
the values at the falling edge
Activate : IN std_logic ;
-- At rising edge of Activate the system input is acquired
VP_ADC : IN std_logic_vector(9 downto 0);
-- The ADC outof the poly resistance voltage
VH_ADC : IN std_logic_vector(9 downto 0);
-- The ADC outof the heater resistance voltage
Sys_input: IN std_logic ; -- The system serial input
Vctrl_DAC : inout std_logic_vector (9 downto 0)
-- TheDAC input of the control voltage
);
end;
-- ---------------------------------------
Architecture behavioral of system_temp_ctrl is
-- ---------------------------------------

PROCEDURE Shift ( num_shift : IN INTEGER ;
-- numbers of bits to shift
z : INOUT STD_LOGIC_VECTOR ((m-1) DOWNTO 0)) IS
VARIABLE i : INTEGER;
VARIABLE T : STD_LOGIC_VECTOR ((m-1) DOWNTO 0);

BEGIN
FOR i IN 0 TO ((m-1)) LOOP T(i) := '0'; END LOOP;
FOR i IN 0 TO ((m-1)-num_shift) LOOP T(i+num_shift):= z(i);
END LOOP;
FOR i IN 0 TO ((m-1)) LOOP z(i) := T(i); END LOOP;
END;

PROCEDURE Shift_right ( num_shift : IN INTEGER ;
-- numbers of bits to shift right
z : INOUT STD_LOGIC_VECTOR ((m-1) DOWNTO 0)) IS
VARIABLE i : INTEGER;
VARIABLE T : STD_LOGIC_VECTOR ((m-1) DOWNTO 0);

BEGIN
FOR i IN 0 TO ((m-1)) LOOP T(i) := '0'; END LOOP;
FOR i IN 0 TO ((m-1)-num_shift) LOOP T(i) := z(i+num_shift); END
LOOP;
FOR i IN 0 TO ((m-1)) LOOP z(i) := T(i); END LOOP;
END;

PROCEDURE Shift_right_n ( num_shift : IN INTEGER ;
-- numbers of bits to shift right
z : INOUT STD_LOGIC_VECTOR ((n-1) DOWNTO 0)) IS
VARIABLE i : INTEGER;
VARIABLE T : STD_LOGIC_VECTOR ((n-1) DOWNTO 0);

BEGIN
FOR i IN 0 TO ((n-1)) LOOP T(i) := '0'; END LOOP;
FOR i IN 0 TO ((n-1)-num_shift) LOOP T(i) := z(i+num_shift);
END LOOP;


Page 120

APPENDIX B: VHDL Codes 107

FOR i IN 0 TO ((n-1)) LOOP z(i) := T(i); END LOOP;
END;

PROCEDURE convert ( A : IN STD_LOGIC_VECTOR ((m-1) DOWNTO 0);
-- Converts m-bits numbers into n-bits
B : out STD_LOGIC_VECTOR ((n-1) DOWNTO 0))IS
variable Temp_n : STD_LOGIC_VECTOR ((n-1) DOWNTO 0);
variable Temp_m : STD_LOGIC_VECTOR ((m-1) DOWNTO 0);
variable zeros_n: STD_LOGIC_VECTOR ((n-1) DOWNTO 0);

BEGIN
for i in 0 to (m-1) loop Temp_m(i):='0'; end loop;
-- generate 0's vector
Temp_m:= std_logic_vector( signed(Temp_m) - signed(A));
--Generate 2's complement
FOR i IN 0 TO (n-1) LOOP Temp_n(i) := Temp_m(i);
zeros_n(i):= '0'; -- generate n 0's
END LOOP;
Temp_n:= std_logic_vector( signed(Zeros_n) - signed(Temp_n));
B:= Temp_n;
END;

PROCEDURE convert_n_to_m
( A : IN std_logic_vector ((n-1) downto 0) ;
-- numbers to be converted
B : out std_logic_vector ((m-1) downto 0) )
-- Output number
Is

variable Temp_n : STD_LOGIC_VECTOR ((n-1) DOWNTO 0);
variable Temp_m : STD_LOGIC_VECTOR ((m-1) DOWNTO 0);
variable zeros_m: STD_LOGIC_VECTOR ((m-1) DOWNTO 0);

BEGIN
if (A(n-1)= '0') then
FOR i IN n TO (m-1) LOOP B(i) := '0'; END LOOP;
-- generate 0's at most significant bits
FOR i IN 0 TO (n-1) LOOP B(i) := A(i); ENDLOOP;
-- copy A into B
else
FOR i IN 0 TO (n-1) LOOP Temp_n(i) := '0';END LOOP;
-- generate 0's vector
Temp_n:=std_logic_vector(Signed(Temp_n)-signed(A));
--Generate 2's complement
FOR i IN n TO (m-1) LOOP Temp_m(i) := '0';END LOOP;
-- generate 0's at most significant bits
FOR i IN 0 TO (n-1) LOOP Temp_m(i) := Temp_n(i); END LOOP;
-- copy (-A) into Temp_m
FOR i IN 0 TO (m-1) LOOP zeros_m(i) := '0';END LOOP;
--- Generate 0's vector
B:= std_logic_vector(signed(zeros_m)-signed(Temp_m));
end if;
END;
procedure divide (A : in std_logic_vector ((m-1) downto 0);
-- division algorithm
B : in std_logic_vector ((n-1) downto 0);
Y : out std_logic_vector ((m-1) downto 0)) is
variable A_signed : signed ((m-1) downto 0);
variable B_signed : signed ((n-1) downto 0);

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