High-speed CMOS dual-modulus presalers for frequency synthesis
transceivers. An important objective of the electronics and communications industry is
to design high-speed building blocks which dissipate the lowest possible power, and to ac-
complish this with the cheapest technology. The dual-modulus prescaler is one of the key
components of a PLL-based frequency synthesizer, operating at gigahertz frequencies.
While several previous implementations have utilized the advantages of a high-speed, but
expensive technology, the growing trend towards integrating the frequency synthesizer
on a single chip is the motivation behind silicon-CMOS implementations. This thesis
addresses the issues in the design of CMOS prescalers for frequency synthesis. A design
methodology is obtained to improve the performance of integrated prescalers using the
current mode style of operation. An 8/9 dual-modulus prescaler prototype has been
designed to obtain speeds of the order of 2.5-3 GHz while minimizing the power con-
sumed to 2.5 mW. The circuit was implemented in a 0.25µm National BiCMOS process.
Measurement results of the prototype have also been obtained.
Advisor:Moon, Un-Ku; Mayaram, Karti; Liu, Huaping; Nibler, Joseph
School:Oregon State University
School Location:USA - Oregon
Source Type:Master's Thesis
Keywords:metal oxide semiconductors complementary electronic circuit design phase locked loops frequency synthesizers
Date of Publication:10/01/2003