Frequency Dividers Design for Multi-GHz PLL Systems

by Barale, Francesco

Abstract (Summary)
In this work, a programmable frequency divider suitable for millimeter wave phase-lock loops is presented. The frequency divider has been implemented in a 90 nm standard CMOS technology. To the extent of maximizing the operative input frequency, the higher frequency digital blocks of the frequency divider have been realized using dynamic precharge-evaluation logic. Moreover, a non-conventional method to implement non-power-of-2 division ratios has been used for the higher frequency divider stages (input stages).
Bibliographical Information:

Advisor:Laskar Joy; Cressler John; Tentzeris Emmanouil

School:Georgia Institute of Technology

School Location:USA - Georgia

Source Type:Master's Thesis

Keywords:electrical and computer engineering


Date of Publication:06/16/2008

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