Force-directed instruction scheduling for low power [electronic resource] / by Prashant Jayawant Dongale.
ABSTRACT: The increasing need for low-power computing devices has led to the efforts to optimize power in all the components of a system. It is possible to achieve significant power optimization at the software level through instruction reordering during the compilation phase. In this thesis, we have designed and implemented a novel instruction scheduling technique, called FD-ISLP, aimed at reducing the software power consumption. In the proposed approach for instruction scheduling, we modify the force-directed scheduling technique used in high-level synthesis of VLSI circuits to derive a latency-constrained algorithm that reorders the instructions in a basic block of assembly code in application software to reduce power consumption due to its execution. The scheduling algorithm takes the data dependency graph (DDG) for a given basic block and a power dissipation table (PDT), which is generated by characterizing the instruction set architecture.
School:University of South Florida
School Location:USA - Florida
Source Type:Master's Thesis
Keywords:optimization estimation dissertations academic usf computer science masters
Date of Publication:01/01/2003