Flexible sigma delta time-interleaved bandpass analog-to-digital converter

by McGinnis, Ryan Edward

McGinnis, Ryan. M.S.Egr., Department of Electrical Engineering, Wright State University, 2006. Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter. Conversion of analog signals to their digital equivalent earlier in a circuit’s topology facilitates faster and more efficient exploitation of the information contained within. Analog-to-digital converters (ADCs) form the link between the analog and digital realms. In high frequency circuits ADCs must often be implemented further downstream after several stages of down-conversion, or through the use of more expensive technologies such as Bi-polar Junction Transistors or Gallium Arsenide. This thesis presents a technique to utilize Complimentary Metal Oxide Semiconductor technology in a parallel timeinterleaved architecture. This will reduce circuit complexity and allow the ADC to be placed further upstream reducing the need for large and expensive analog hardware. This thesis utilizes an architecture that allows for higher frequency input signals through the use of downsampling, parallel processing, and recombination. This thesis will also present the use of sigma delta based modulation in order to increase the resolution of the digital output signal. Exploitation of oversampling and the resultant noise-shaping characteristics of the sigma delta modulator will enable the user to gain resolution without the increased cost of implementing more expensive ADC architectures such as Flash. iii This thesis also presents a flexible converter such that both the center frequency and resolution can be modified by manipulating inputs. Specifically, the input and output filters as well as the sampling frequency can be tuned such that the circuit will operate at a particular center frequency. Also, the circuit will have flexible resolution which can be controlled by the clock input. Proof of concept is accomplished with a Matlab® simulation followed by schematic implementation in Cadence®. The design is constructed using IBM® 0.13 µm technology with a rail voltage of 1.2 V. Results are evaluated through the calculation of the effective number of bits and the signal to noise ratio. Conclusions and guidance on future research are provided. iv