Fabrication and device characterization of alternative gate stacks using the non self-aligned gate process

by 1971- Han, Sungkee

HAN, Sungkee. Fabrication and Device Characterization of Alternative Gate Stacks Using the Non Self-Aligned Gate Process (Under the direction of Carlton M. Osburn) In order to improve MOSFET transistor performance, aggressive scaling of devices has continued. As lateral device dimensions continue to scale down, gate oxide thicknesses must also be scaled down. According to the 2001 International Technology Roadmap for Semiconductor (ITRS) for sub-micron technology, an equivalent oxide thickness (EOT) less than 1.0 nm is required for high performance devices. However, at this thickness SiO2 has reached its scaling limit due to the high tunneling current, especially in low power devcies. The use of high K dielectrics may circumvent this impediment since physically thicker dielectrics can be used to reduce gate leakage while maintaining the same level of inversion charge. In this study, we used an alternative, non self-aligned gate process to fabricate both NMOS and PMOS devices with a variety of high K gate dielectric and metal gate electrode materials; finally their electrical properties were characterized. Most high K gate dielectric and gate metal candidates have limited thermal stability. As a result, conventional transistor fabrication process flows cannot be used. Here we developed a non self-aligned gate process, which reverses the order of the junction and the gate stack formation steps and thus allow the use of dielectrics and electrode materials that are not able to sustain high junction activation temperatures. A new mask set, ERC-6, was designed to facilitate the non-self aligned gate process. Wet and dry etching process for alternative high K gate dielectrics (HfO2, ZrO2, La2O3, Y2O3) and metal gate electrodes (Pt, Ru, RuO2, Ta, TaN) were studied. Wet etching of Pt and TaN required periodic re-baking of the photoresist to re-establish adhesion to the substrate. Reactive ion etch (RIE) processes were developed for RuO2, Ru/W, Ta/W gate electrodes. A mixture of oxygen and fluorine plasma was effective in patterning RuO2 electrodes. However, for Ru gate electrodes, etch rates only up to 6.7 nm/min could be obtained even with the optimized addition of a few percent Cl2 to O2; this etch rate was considerably slower than that of photoresist. Rather than using a hard mask to etch the Ru gate, a laminated gate composed of a thin Ru layer (3 nm) covered with a thicker W film (100 nm) was successfully dry etched. The etching characteristics of various high K gate dielectrics depended not only on the materials, but also on how they were deposited, including the substrate pretreatment and post deposition anneal conditions. For instance, jet vapor deposited (JVD) HfO2 would etch in BOE (10% HF), while other HfO2 films required dry etching. Similarly, rapid thermal CVD (RTCVD) ZrO2 required dry etching while other ZrO2 films could be wet etched in BOE. The electrical properties, including capacitance vs. voltage (C-V), gate leakage current (Ig-Vg), drain current vs. gate voltage (Id-Vd) and drain current vs. drain voltage (Id-Vd) characteristics, were measured on devices having a variety of high K gate dielectrics and gate metal electrodes. These electrical measurements were used to compare not only the different higk K dielectrics but also the different deposition systems. First, oxide control devices were fabricated to produce baseline data and to verify the non self-aligned process. The gate leakage current and channel mobility of the 1 nm thick control oxides were in good agreement with previously reported values. Reasonably good C-V characteristics were observed for HfO2 (JVD) and ZrO2 (JVD and RTCVD) except for the devices having TaN gate electrodes. Due to over-etching, a large die-todie variability was observed with TaN gated capacitors. The measured EOT values for HfO2 and ZrO2 films ranged from 1.28 to 2.25 nm and 1.86 to 2.62 nm, respectively. The