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FPGA logic design for analog-to-digital-converter hardware utilizing high speed serial data links [electronic resource] /

by Jones, Joshua Brandon

Abstract (Summary)
The Computer Assisted Dynamic Data Monitoring and Analysis System (CADDMAS) used by the aeropropulsion test cells at Arnold Engineering Development Center (AEDC) processes a large amount of high bandwidth accelerometer and strain gage data. Data from each sensor must be digitized before being processed by software running on networked computers. This thesis describes some of the original analog-todigital converter (ADC) hardware used by the CADDMAS as well as some of its limitations. More up-to-date ADC hardware was designed to be used in the CADDMAS to enhance capabilities required by the aeropropulsion test cells. These new capabilities included an increase in maximum sample rate for the CADDMAS, a Universal Serial Bus (USB) 2.0 interface for easy connection to the computer, the latest Field Programmable Gate Arrays (FPGAs) for controlling the data acquisition, and a packet based data transmission scheme to reduce redundant data transfers into the computer. This thesis describes, in detail, the development and checkout of the FPGA logic for the new ADC hardware needed to obtain these enhanced capabilities. A simple software program was also developed to validate the correct operation of the new ADC hardware and to demonstrate to a commercial software vendor how to incorporate support for the ADC hardware into their software. Upon completion of the designs, a maximum data transfer rate of 96.15 Megabytes per second (MBps) was obtained using a PCI interface card and 18.45 MBps was obtained from the USB 2.0 interface.
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School:The University of Tennessee at Chattanooga

School Location:USA - Tennessee

Source Type:Master's Thesis

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