Evaluation, Optimization,and Reliability of No-flow Underfill Process
This research details the development of a novel process for four commercially available no-flow fluxing underfills for use with flip chip on FR4 substrates. The daisy chain test die was used such that two point resistance measurements could be used to determine the integrity of the solder interconnects post reflow. The impact of the underfill dispensing pattern on underfill void formation is determined in a full factorial dispense DOE that includes two factors: pattern and speed. Evaluation metrics include underfill material voiding and fillet shape. The impact of the placement process is determined in a second full factorial DOE involving three factors at two levels each: dispense pattern, placement force, and dwell time. Metrics include interconnect yield and underfill voiding. The results of these DOEs are used to select an optimal placement process for each material to be used for the remaining reflow experiments. The process developed is a novel approach to no-flow processing; the material is dispensed to the side of the bond site and allowed to flow under the chip after placement by capillary action during the early stages of reflow. This development allows for void free assemblies using no-flow materials. Reflow parameters are investigated using a parametric approach. The following parameters are varied at 2 levels individually off a baseline profile: Peak Temperature, Time > 183 oC, Peak Ramp Rate, Soak Time, and Soak Temperature. A ranking was developed for each material based on the observable metrics: interconnect yield, underfill material voiding, two point resistance, and a grain area fraction term. The results were used to select an optimal assembly process for each material. Test boards were assembled in replicates of 30 according to the optimal process for each material, and AATC -40 to 125 oC thermal cycling test was performed. The MTTF for these assemblies has exceeded 3000 cycles; the void free process successfully avoids premature failure due to solder extrusion into voids. Further process development work has demonstrated that the process is scalable to larger area array die and other edge dispense patterns have also been demonstrated to result in void free assemblies.
Advisor:Daniel Baldwin; Suresh Sitaraman; Steven Danyluk
School:Georgia Institute of Technology
School Location:USA - Georgia
Source Type:Master's Thesis
Date of Publication:01/28/2004