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Etch rate modification by implantation of oxide and polysilicon for planar double gate MOS fabrication

by Charavel, Rémy

Abstract (Summary)
In the context of transistor size miniaturization the motivation of this work was focused on the fabrication process of planar double gate devices. We proposed in this work three process flows based on the use of buried mask which could allow the fabrication of self-aligned planar double gate transistors. The novel concept of buried mask consists into modifying the etch rate of a buried polysilicon or oxide layer. This etch rate modification being defined by ion implantation, etch stop or scacrificial zones aligned with the implantation mask can thus be fabricated. This technique solve the alignment of the front and back gate. Ion implantation causes damages to the implanted target, and is used to dope semiconductor material. If the implanted atoms have a small radii they can induce stress to the implanted lattice. These three consequences of ion implantation, damage, doping and stress are used to modify the etch rate of oxide and polysilicon. High etching selectivity are reached, which allow the fabrication of a localized buried sacrificial or etch stop zone, called buried mask. The definition of the buried mask being done by ion implantation, it opens the possibility to fabricate a buried mask aligned with the implantation mask. Although some more work has to be invested to fabricate planar double gate MOS using buried mask in polysilicon, this concept of buried mask, which could also be called anisotropic wet and vapor etching, is foreseen as a very promising technique in MEMS micromachining and for bio sensor applications.
Bibliographical Information:

Advisor:

School:Université catholique de Louvain

School Location:Belgium

Source Type:Master's Thesis

Keywords:ion implantation etch rate modification planar double gate buried mask etching selectivity

ISBN:

Date of Publication:01/31/2007

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