EDGE TERMINATION AND RESURF TECHNOLOGY IN POWER SILICON CARBIDE DEVICES
The effect of the electrical field enhancement at the junction discontinuities and its impact on the on-state resistance of power semiconductor devices was investigated. A systematic analysis of the mechanisms behind the techniques that can be used for the edge termination in power semiconductor devices was performed. The influence of the passivation layer properties, such as effective interface charge and dielectric permittivity, on the devices with different edge terminations was analyzed using numerical simulation.
A compact analytical expression for the optimal JTE dose was proposed for the first time. This expression has been numerically evaluated for different targeted values of the blocking voltage and the maximum electric field, always resulting in the optimal field distribution that does not require further optimization with 2-D device simulator. A compact set of rules for the optimal design of super-junction power devices was developed. Compact analytical expressions for the optimal dopings and dimensions of the devices employed the field compensation technique are derived and validated with the results of numerical simulations on practical device structures.
A comparative experimental study of several approaches used for the edge termination in SiC power diodes and transistors was performed. The investigated techniques included the mesa termination, high-k termination, JTE, and the combination of JTE and field plate edge termination. The mesa edge termination was found to be the most promising among the techniques investigated in this work. This stand-along technique satisfied all the imposed requirements for the ?ideal? edge termination: performance, reproducibility (scalability), and cost-efficiency. First of all, it resulted in the maximum one-dimensional electric field (E1DMAX) at the main device junction equal to 2.4 MV/cm or 93% of the theoretical value of critical electric field in 4H-SiC. Secondly, the measured E1DMAX was found to be independent of the voltage blocking layer parameters that demonstrate the scalability of this technique. Lastly, the implementation of this technique does not require expensive fabrication steps, and along with an efficient use of the die area results in the low cost and high yield.
Advisor:Dr. Yaroslav Koshka; Dr. Yaroslav Koshka; Dr. Yaroslav Koshka; Dr. Yaroslav Koshka
School:Mississippi State University
School Location:USA - Mississippi
Source Type:Master's Thesis
Keywords:electrical and computer engineering
Date of Publication:12/16/2005