DEVELOPMENT OF DIGITAL AND MIXED SIGNAL STANDARD CELLS FOR A 0.25µm CMOS PROCESS

by MADHUSUDANAN, RAHUL

The competitiveness of the semiconductor market makes the tradeoffs between performance, cost and time to market very crucial. The current scenario is such that the non-recurring expenses involved in the design process, like design and tooling costs, dwarf the actual cost of producing the chip; termed as the recurring expenses. Unfortunately, high non-recurring costs can make it impossible for many smaller companies to remain profitable. The standard cell library used in higher-level synthesis and placement steps is one of the significant cost incurring steps of the design flow. The proposed thesis develops a 32-cell library for the TSMC quarter micron process using a unique and cost effective design flow, where only non-commercial tools available in the open domain are used. The custom design flow used is discussed in detail. An overview of other similar CAD resources available in the open domain is also presented. Such a flow, although time intensive, is a cost effective alternative for smaller ventures.