Design and implementation of a sub-threshold wireless BFSK transmitter

by Paul, Suganth

Abstract (Summary)
Power Consumption in VLSI (Very Large Scale Integrated) circuits is currently a major issue in the semiconductor industry. Power is a first order design constraint in many applications. Several of these applications need extreme low power but do not need high speed. Sub-threshold circuit design can be used in these cases, but at such a low supply voltage these circuits exhibit an exponential sensitivity to process, voltage and temperature (PVT) variations. In this thesis we implement and test a robust sub-threshold design flow which uses circuit level PVT compensation to stabilize circuit performance. This is done by dynamic modulation of the delay of a representative signal in the circuit and then phase locking it with an external reference signal. We design and fabricate a sub-threshold wireless BFSK transmitter chip. The transmitter is specified to transmit baseband signals up to a data rate of 32kbps over a distance of 1000m. In addition to the sub-threshold implementation, we implement the BFSK transmitter using a standard cell methodology on the same die operating at super-threshold voltages on a different voltage domain. Experiments using the fabricated die show that the sub-threshold circuit consumes 19.4x lower power than the traditional standard cell based implementation.
Bibliographical Information:

Advisor:Khatri, Sunil, P; Li, Peng; Walker, Duncan, M

School:Texas A&M University

School Location:USA - Texas

Source Type:Master's Thesis

Keywords:sub threshold wireless bfsk transmitter programmable logic arrary adaptive body bias


Date of Publication:12/01/2007

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