Design of high-performance pipeline analog-to-digital converters in low-voltage processes

by Myers, Charles Grant

Pipeline analog-to-digital converters (ADCs) have long been used in high-speed

systems for power-efficient data conversion. Broadband communication and video processing systems are placing high demands on converter accuracy and speed (above 14 bits

and in the multiple-MHz range). The increasing converter requirements coupled with

lower supply voltages in modern processes makes designing pipeline ADCs to meet these

requirements exceedingly difficult.

This thesis addresses the issues associated with designing a pipeline ADC for high

accuracy under modern low-voltage process limitations. Fundamental barriers to an

economical solution at this accuracy level, such as kT/C thermal noise, are addressed

through system and circuit level design. These include such concepts as rail-to-rail

inputs for improved signal power and sample-and-hold (S/H) removal for noise and

power savings.

The presented concepts are combined in a prototype design implementation using

a 0.18?m, 1.8V process. This serves as a platform for addressing issues with integrating

the ideas simultaneously. Simulations and modeling presented illustrate the feasibility

of such a design.