DESIGN OF AN INPUT/OUTPUT BLOCK FOR A MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY
Abstract (Summary)As the name suggests this thesis is a part of development of a Mutli-Technology FPGA (MT-FPGA). The present FPGAs do not facilitate the prototyping of designs with Multi Technology blocks like MEMS and photonic devices, which are currently a rapidly growing technology. The proposed MT-FPGA incorporates multi technology blocks in the traditional well-developed FPGAs, confined to electronics. This thesis mainly concerns the development of an Input/Output block (I/O Block) for the proposed MT-FPGA. The need of I/O block arises due to the limitation of the available pins at the periphery of the chip. The thesis deals with the design of a circuit to overcome this pin-limitation. The MT-FPGA chip design was fabricated through MOSIS foundry in TSMC 0.35um technology. The testing of this chip is discussed in the later part of the thesis. Due to the design errors discovered during testing, the characterization of the MT-FPGA was not realized.
School:University of Cincinnati
School Location:USA - Ohio
Source Type:Master's Thesis
Date of Publication:01/01/2004