Design and analysis of agile frequency synthesizers for mobile communications
Abstract (Summary)The wireless market has experienced an exponential growth over the past few years. To sustain this growth dong with the increasing demands of new wireless standards, the cost, battery lifetime, and performance of wireless devices must all be enhanced. With the advancernent of radio fiequency (RF) technology and requirement for more integration, new RF wireless architectures are needed. One of the most critical components in a wireless transceiver is the fkequency synthesizer. It largely affects all three dimensions of a wireless transceiver design: cost, battery lifetime, and performance. In this thesis, new generations of RF synthesizer and transmitter architectures allowing low-power, high-performance and lower cost are presented. The common approach to fiequency synthesis design for wireless communication is to design an analog-compensated fractional-N phase-Iocked Ioop (PLL) . However, this technique suffers fiom lock time limitations and lack of adequate fractional spur suppression for third generation wireless standards. In this work, two new fast lock PLL architectures are reported to overcome the above mentioned limitations with the aid of digital signal processing. One such scheme makes use of modified digital sigmadelta modulator to cornpletely randomize fiactional spurs present in fractional-N PLLs as well as to reduce the level of phase noise produced by the sigma-delta modulator. This aids in fully integrating a high-performance PLL frequency synthesizer, and hence reducing cost. The use of this architecture for closed loop modulation is also examined. In another approach, a high frequency digital comparator aids in quickly acquiring fiequency lock. Very fast lock tixnes are achievable using this architecture. This architecture removes the PU'S fiequency resolution dependence on the loop fdter parameters. This helps to drastically reduce the size of the loop filter components, and enables them to be integrated on-chip. Although more suitable for low fiequency resolution applications, such as wkeless LAN and cordless, this architecture may be modified to obtain higher fiequency resolutions. The major advantages of this architecture hclude low-cost, low-power, and a fully monolithic solution. Throughout this work, Iow-pwer has been achieved by both architectural techniques as weH as circuit techniques. Architectural techniques enable tighter integration of the PLL's loop components on a single chip as well as faster lock tirne. Since the proposed techniques rely heavily on digital signal processing, low-power, high-performance digital logic families are reported. It is demonstrated how these logic famiIies may be used in the fkequency synthesizer architectures detailed above. Although differentid in nature, it is demonstrated that the use of these logic families dso helps to reduce area.
Source Type:Master's Thesis
Date of Publication:01/01/2001