Design of a High Speed Mixed Signal CMOS Mutliplying Circuit Design of a High Speed Mixed Signal CMOS Mutliplying Circuit
This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.
School:Brigham Young University
School Location:USA - Utah
Source Type:Master's Thesis
Keywords:design high speed mixed signal cmos mutliplier circuit short channel pmos transistors mosfet cadence systems nonlinearity filtering digital to analog conversion linear equalization effects
Date of Publication:02/23/2004