Correlation of PDN Impedance with Jitter and Voltage Margin in High Speed Channels
Jitter and noise on package and printed circuit board interconnects are limiting factors in the performance of high speed digital channels. The simultaneous switching noise (SSN) induced by the return path discontinuities (RPDs) is a major source of noise and jitter on the signal interconnects of these channels. Therefore, optimal design of the power delivery network (PDN) is required to reduce SSN induced noise and jitter and improve the performance of high speed channels.
The design of PDN is done in frequency domain whereas jitter and noise are time domain events. As a result, multiple iterations between frequency domain design of PDN and time domain analysis of noise and jitter are required before a design is taped out.
A new methodology to correlate PDN impedance with jitter and voltage margin is presented in this thesis. Using this methodology, it would be possible to estimate jitter and noise from the PDN impedance and reduce the iterations involved in freezing the PDN design.
The SSN induced at a given RPD is proportional to the PDN impedance at that RPD. As a result, the jitter and the noise can be correlated to the PDN impedance. The PDN impedance is a function of frequency and has alternate local minima and local maxima at resonances and anti-resonances respectively. The anti-resonances in the PDN impedance at the RPD cause significant increase in the insertion loss of signal whose return current is disrupted at that RPD. The increase in the insertion loss attenuates significant harmonics of the signal degrading its rise/fall times and voltage levels. This results in
reduction of timing and voltage margins of the signal. Thus, based on the insertion loss profile and harmonic content of the signal, an estimate of jitter and noise on the signal can be made. Passive test vehicles consisting of microstrips with RPDs have been designed and fabricated to demonstrate the proof of concept through both simulations and measurements.
Suitable placement of decoupling capacitors is suggested to reduce the PDN impedance below the target impedance and to minimize coupling between two noise ports on the PDN. Genetic algorithm to optimize the selection and placement of decoupling capacitors has been implemented. The efficacy of the algorithm has been demonstrated by testing it on a power delivery networks consisting of a simple power/ground plane pair.
Advisor:Swaminathan, Madhavan; Keezer, David; Mukhopadhyay, Saibal
School:Georgia Institute of Technology
School Location:USA - Georgia
Source Type:Master's Thesis
Keywords:electrical and computer engineering
Date of Publication:11/19/2008