Clock tree insertion and verification for 3D integrated circuits

by 1981- Mineo, Christopher Alexander

MINEO, CHRISTOPHER ALEXANDER. Clock Tree Insertion and Verification for 3D Integrated Circuits. (Under the direction of Dr. W. Rhett Davis) The use of three dimensional chip fabrication technologies has emerged as a solution to the difficulties involved with the continued scaling of bulk silicon devices. While the technology exists, it is undervalued and underutilized largely due to the design and verification challenges a complex 3D design presents. This work presents a clock tree insertion and timing verification methodology for three dimensional integrated circuits (3DIC). It has been designed in the context of and incorporated into the 3DIC design methodology also developed within our research group. The 3DIC verification methodology serves as an efficient means to perform all setup and hold timing checks harnessing the power of existing commercial chip design and verification tools. A novel approach is presented in which the multi-die design is temporarily transformed to appear as a traditional 2D design to the commercial tools for verification purposes. Various parasitic extraction algorithms are examined, and we present a method for performing accurate 3D parasitic extraction for timing purposes. We offer theoretical insight into the optimization of a 3D clock tree for power savings and coupling-induced delay minimization. A practical example of the 3DIC design and verification flow is detailed through the explanation of our research group’s test chip, a nearly 140,000 cell 3D fast Fourier transform chip currently awaiting fabrication at MIT’s Lincoln Labs. Biography Christopher Alexander Mineo was born on September 19, 1981 in Manhasset, NY. For most of his life he has lived in northern New Jersey with loving parents Ron and Paula, and wonderful sister Kim. Chris received the Bachelor of Engineering degree in Electrical and Computer Engineering with a VLSI concentration from Rutgers, The State University of New Jersey—New Brunswick in 2003. In the fall of 2003 he began the Master of Science in Computer Engineering program at North Carolina State University in Raleigh. Shortly thereafter, he joined the Methodologies for User-friendly System-on-a-chip Experimentation research group under the advisement of Dr. Rhett Davis. Since graduating from Rutgers University, Chris has worked at BAE Systems North America in Wayne, NJ. There he primarily wrote VHDL to program FPGA’s for communication systems. He also works at IBM in Research Triangle Park, NC. At IBM Chris works with both the custom digital circuits VLSI teams and the timing teams on the next generation PowerPC processor. Chris currently works as a research assistant at NC State University on the 3DIC project funded by DARPA. This project involves primarily the design of complex digital systems, design tool modification and development, and design and verification methodology development. ii