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COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs

by BHATTACHARYA, PRASUN

Abstract (Summary)
Systems-on-chip brought several cores onto a single chip. But, as more cores are being put onto a single chip, the on-chip communication resource, which is usually a bus started getting overburdened. With its inherent problems like scaling, inability to support parallelism etc. the on-chip communication soon became a performance bottleneck. Networks-on-chip has been proposed as a solution for on-chip communication. Thus we aim to compare the relative performance of contemporary against indigenously built cores of NoCs. We first built a router keeping in mind the area limitations of FPGAs. Then we extract the timing information by simulations of the Bus and Router cores on FPGAs. Finally, for comparison of buses and NoCs we develop a cycle accurate simulator using the timing values obtained by simulation of the cores. It was developed in C++ for both the bus and the NoC to compare the two on a set of benchmarks.
Bibliographical Information:

Advisor:

School:University of Cincinnati

School Location:USA - Ohio

Source Type:Master's Thesis

Keywords:noc routers soc fpga

ISBN:

Date of Publication:01/01/2006

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