A C to Register Transfer Level Algorithm Using Structured Circuit Templates: A Case Study with Simulated Annealing

by Phillips, Jonathan D.

Abstract (Summary)
A tool flow is presented for deriving simulated annealing accelerator circuits on a field programmable gate array (FPGA) from C source code by exploring architecture solutions that conform to a preset template through scheduling and mapping algorithms. A case study carried out on simulated annealing-based Autonomous Mission Planning and Scheduling (AMPS) software used for autonomous spacecraft systems is explained. The goal of the research is an automated method for the derivation of a hardware design that maximizes performance while minimizing the FPGA footprint. Results obtained are compared with a peer C to register transfer level (RTL) logic tool, a state-of-the-art space-borne embedded processor and a commodity desktop processor for a variety of problems. The automatically derived hardware circuits consistently outperform other methods by one or more orders of magnitude.
Bibliographical Information:


School:Utah State University

School Location:USA - Utah

Source Type:Master's Thesis

Keywords:autonomy complier hardware acceleration space probes


Date of Publication:12/01/2008

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