Abstract (Summary)
Layout-induced parasitics have significant effects on the behavior of circuits in general and the performance of high-frequency analog ones in particular. To achieve parasite-inclusive performance-closure, layout-aware circuit synthesis methodologies are beginning to emerge. In layout-in-the-loop synthesis methodologies, performance analysis is based on the generation of a concrete layout for the explored circuit sizes. A parasite-inclusive circuit is extracted from the layout using a standard extractor and is analyzed using a simulator to determine whether the required constraints are met. The purpose of layout generation during the synthesis process is solely to determine the layout-induced effects in terms of device and interconnect parasites in the extracted circuit in order to perform accurate, layout-aware performance analysis. If the parasites could be estimated or determined otherwise, there would be no need for layout generation. Various approaches of estimating parasitics lack the correctness that would only come from examining the layout itself. The proposed approach tries to include the exactness of the layout to be generated without actually generating it. It relies on using pre-generated structures for the specified un-sized circuit; these structures are generated before synthesis, they contain the information that a layout would have provided to a synthesis process if it was to be generated. This information contains extraction specifics for modules, location of modules and routing characteristics. Pre-Layout Extraction: The concept of Pre-Layout Extraction shall be used to cover the extraction specific information of modules present in the circuit. It is achieved using a high-level language MSL (Module Specification Language) for the specification of parameterized, topology-specific circuit extractors. Upon compilation, the MSL program yields an executable module which generates the extracted circuit containing parasitics, passive and active devices when given specific sizes. This is done without ever generating a layout. Multi-Placement Structures: For the placement specification of the layout, Multi-Placement Structures shall be used. The proposed approach aims at retaining the benefits of both optimization-based techniques and layout templates techniques: a fast instantiation time of layout for layout-inclusive synthesis and various placement possibilities for various input sizes. ( No restriction to a single, pre-defined template ). It consists of a one-time generation of a multi-placement structure for a specific unsized circuit. The obtained structure would be used in a layout-inclusive synthesis process in the following manner: It is provided with numerical sizes from a sizing algorithm tool and returns a specific floor-plan for the circuit. For different sizes given, the aim is to have the best floor-plan returned depending on the specified sizes. Multi-Variant Routing: The remaining part of a layout description known as routing shall be handled using the proposed idea of Multi-Variant Routing. This method follows the same line of thought as its corresponding one in the placement field. It consists of a one-time generation of a Multi-Variant Routing Structure that would instantiate distinct routing schemes for distinct specified sizes and modules positions. Depending on the size of the modules in the circuit, and on their locations instantiated using the Multi-Placement Structure, the Multi-Variant Routing Structure shall be able to produce the most efficient routing scheme for the proposed circuit. Its power relies on a one-time intelligent search accomplished before synthesis, while building the structure. Depending on the locations and the sizes of the modules in the circuit, the nets in the circuit are attached to a multiple-possibility path that is controlled by the dynamic feature of changin channels and blocks’ sizes. The combination of these three described novel methods of layout approaches can be very beneficial to the synthesis of circuits and specially analog ones. It is expected to introduce a speedup factor varying from 4 to 5 with comparison to layout-inclusive synthesis approaches while having the quality of layout exploration not found in template-based approaches.
Bibliographical Information:


School:University of Cincinnati

School Location:USA - Ohio

Source Type:Master's Thesis

Keywords:vlsi analog routing placement extraction pre layout


Date of Publication:01/01/2005

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